lfsr  2,0x080                  ;Initialize queue input pointer, FSR2
        MOVLF  0x80,GETPTRL            ;Initialize queue output pointer, GETPTRL


;(a) Initialization


PUT     macro
        movwf  INDF2                   ;Put WREG into queue
        incf  FSR2L,F                  ;Increment pointer,
        bsf  FSR2L,7                   ; constraining result to B'1xxxxxxx' addresses
        endm


;(b) PUT macro


;;;;;;; Get subroutine ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; If queue is empty, this subroutine returns with Z=1.
; If queue is not empty, it returns with Z=0 and with byte in WREG.
; It stores the queue output pointer in GETPTRL.
; It uses RAM ranging from 0x080 to 0x0ff for the queue.

Get
        movf  FSR2L,W                  ;Compare lower eight bits of pointers
        subwf  GETPTRL,W
        ;IF_  .NZ.
        bz	L1
          movff  GETPTRL,FSR0L         ;Load pointer into  FSR0H:FSR0L
          clrf  FSR0H
          movf  INDF0,W                ;Get byte
          incf  FSR0L,F                ;Increment pointer,
          bsf  FSR0L,7                 ; constraining result to B'1xxxxxxx' addresses
          movff  FSR0L,GETPTRL         ;Return pointer to RAM
          bcf  STATUS,Z                ;Return from subroutine with Z=0
        ;ENDIF_
L1
        return


;(c) Get subroutine


;Figure 18-9   Queue implementation.




        bsf     RCON,IPEN              ;Enable priority levels
        bsf     IPR1,RCIP              ;Receive interrupts have high priority
        bcf     PIR1,RCIF              ;Clear flag
        bsf     PIE1,RCIE              ;Enable local interrupt source
        bsf     INTCON,GIEH            ;Enable all interrupts globally


;(a) Initialization of UART "receive" high-priority interrupts


        org  0x0008
HiPriISR                               ;2 cycles to get from interrupted code
        movf  RCREG,W                  ;1 cycle (flag automatically cleared by read)
        PUT                            ;3 cycles
        retfie  FAST                   ;2 cycles


;(b) Interrupt service routine


;Figure 18-10 UART high-priority interrupt service routine.